The JanusII Special Purpose Computer is the  second generation supercomputer located at BIFI. As its predecessor, JanusII was designed as a multipurpose reprogramable supercomputer, also based on reconfigurable FPGA processors. 

JanusII was born during the summer of 2013 as the second high challenging project of the Janus Collaboration. Following the same successful Janus philosophy, JanusII is composed again by 16 boards. On each board, 16 latest generation FPGA processors (Xilinx Virtex-7 XC7VX485T FPGA) are located and linked obeying periodic boundary conditions. They are called SP’s from “Simulation Processor”, since they will be in charge of the simulations.

On each board, 16 latest generation FPGA processors (Xilinx Virtex-7 XC7VX485T FPGA) are located and linked obeying periodic boundary conditions. They are called SP’s from “Simulation Processor”, since they will be in charge of the simulations. All SP’s on each board are controlled by a full fledged computer that we call CP (Control Processor), running the Linux operating system. These CP’s configure all FPGA processors for the simulations, controlling and monitoring their status. The CP uses a commercially available Computer-on-Module system (COM), based on an Intel Core i7 processor; it connects via the PCIe interface to a so-called Input-Output-Processor (IOP) built inside yet another FPGA. The IOP actually manages all connections to all SP’s, controlling the configuration procedure and their operation, and monitoring their status.

The Janus II architecture includes also improved communications, permitting the interconnection between all boards, and it enlarges 100 times the memory available.

Thanks to the new topology and improved performance, JanusII has allowed us to study much larger systems, increasing the simulation time and the number of samples achieved so far even with Janus.

In order to see a complete list of the Janus Collaboration publications, please visit the Publication Section of Janus and JanusII.

 

 

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JanusII was built thanks to FEDER funds: Ministerio de Economía y Competitividad (Gobierno de España) and Gobierno de Aragón, supported in collaboration with the European Union.